1. Field of the Disclosed Embodiments
The disclosed embodiments relate to semiconductor device fabrication, and more particularly to a method and apparatus for processing of semiconductor substrates.
2. Brief Description of Earlier Developments
Integrated circuits are generally built on a silicon wafer base and include many components such as transistors, capacitors and other electronic devices connected by multiple layers of wiring, or interconnect. Most advanced chips are now constructed with copper interconnects, since copper has lower resistivity than aluminum. These interconnects are often multi-level and are formed by filling high-aspect ratio features, such as vias and trenches. These features are filled first with dielectric barrier layers followed by metal seed layers using either physical vapor deposition (PVD) or chemical vapor deposition (CVD). After the seed layer, the interconnect features are filled with copper using electrochemical plating (ECP). This process sequence is used for front-end-of-line applications such as copper damascene interconnects and also for the larger interconnects used in advanced packaging. Alternate process sequences are also under development to eliminate the need for seed layers and allow direct electro-plating on silicon or on barrier materials.
Copper damascene and direct plating processes use one or more anneal steps to improve interconnect properties and to facilitate further processing. Anneal is used to increase electrical conductivity via grain refinement, to reduce via pullout and voids via stress relaxation and to reduce the possibility of failures due to electro-migration. Annealing leaves the copper in a known state, which is necessary for reliable down-stream processing. For example, having a known, uniform state of hardness and grain size is required to achieve stable process control for chemical-mechanical-polishing (CMP), the most common post-plating process step.
Semiconductor annealing can be performed by a variety of equipment. Anneal equipment include ovens, vertical furnaces, rapid thermal processing systems and specialized modules. Furnaces and other dedicated external anneal system have the disadvantage that they require additional wafer handling, as the wafers are transported to the dedicated tool in a specialized carrier. Specialized modules may be directly attached to electro-plating tools. Directly attached modules have the advantage that anneal can be incorporating directly into the electro-plating recipe, and wafers can be annealed one or more times as necessary during plating.
Annealing may be typically done for several minutes at a temperature of 200-400° C. Annealing may be performed in an inert or reducing gas atmosphere to prevent oxidation. The most common atmosphere is nitrogen, although forming gas (a mixture of nitrogen and hydrogen) is sometimes used. Wafers are typically brought to the anneal temperature by placing them close to a heated chuck for a recipe-dependent time. Wafers are then cooled either by natural convection or by contact with a cool surface. They are then returned to a cassette or specialized enclosure and transported to the next processing tool.
Anneal chambers for semiconductor processing may be divided into two types based on their geometry. Vertical anneal chambers have their heating area vertically below their cooling area. Horizontal anneal chambers have their heating area horizontally adjacent their cooling area. A representative vertical geometry anneal chamber with a heating area below the cooling area is described, for example, in U.S. Pat. No. 6,929,774 by Morad et. al. A representative horizontal anneal chamber with a heating area horizontally adjacent to a cooling area is described in U.S. Pat. No. 7,311,810 by Mok et al., both of which are incorporated by reference herein in their entireties.